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[VHDL-FPGA-Verilog] dds

Description: dds 驱动 ad9851 fpga vhdl-ad9851 dds ad9851 fpga vhdl
Platform: | Size: 1544192 | Author: ZHANGLONG | Hits:

[VHDL-FPGA-Verilog] DDS_FINAL

Description: My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wave and saw wave with different frequency. We can change the frequency using frequency selector input. Please accept this project. We use the SPARTAN 3E 500 device to implement it.
Platform: | Size: 437248 | Author: Raju Kumar | Hits:

[VHDL-FPGA-Verilog] dds

Description: 这是用VERILOG描写的一个DDS的实例，涉及到一些lpm的运用希望对大家有用-it‘s useful。
Platform: | Size: 881664 | Author: tom | Hits:

[VHDL-FPGA-Verilog] DDS_VERILOG

Description: verilog dds 在发生正弦波时，很好的参考代码-verilog dds
Platform: | Size: 3072 | Author: 王洋 | Hits:

[VHDL-FPGA-Verilog] dds_final

Description: 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjustable modulation. DA-chip 8-bit parallel, 160MHz
Platform: | Size: 1638400 | Author: nostalgia | Hits:

[VHDL-FPGA-Verilog] DDS_Set

Description: AD9852，DDS芯片接收数据逻辑。（Verilog语言）-AD9852, DDS chips receive data logic. (Verilog language)
Platform: | Size: 1024 | Author: zhangwei | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 在FPGA中实现频率源的设计,使用硬件描述语言加以实现。-design DDS with verilog language
Platform: | Size: 125952 | Author: lin | Hits:

[VHDL-FPGA-Verilog] dds

Description: 用Verilog语言实现基于dds技术的余弦信号发生器，其输出位宽为16比特-Dds with the Verilog language technology based on the cosine signal generator, the output bit width is 16 bits
Platform: | Size: 8192 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] DDS__FPGA

Description: 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容
Platform: | Size: 92160 | Author: 小何 | Hits:

[VHDL-FPGA-Verilog] dds-design

Description: fpga实现dds，实现任意波形输出信，设计代码verilog-dds fpga realization
Platform: | Size: 1024 | Author: cc | Hits:

[VHDL-FPGA-Verilog] ddsfinal1

Description: verilog语言实现的dds代码，并行通信，生成四种波形，大赛编写的代码，modelsim仿真-verilog language dds code,modelsim debug
Platform: | Size: 1137664 | Author: 杨天 | Hits:

[VHDL-FPGA-Verilog] dds

Description: 采用verlog编写的tlc5615驱动程序，并利用了rom核实现了dds功能-Using verlog written tlc5615 driver, and use the rom-core functions to achieve a dds
Platform: | Size: 619520 | Author: ranshaoqiang | Hits:

[VHDL-FPGA-Verilog] Verilog-dds

Description: 用Verilog实现的DDS，直接频率合成器，相位可调。-Verilog DDS generator
Platform: | Size: 1184768 | Author: fu | Hits:

[VHDL-FPGA-Verilog] DDS-Verilog-design-and-simulation

Description: DDS的Verilog设计及QuartusⅡ与Matlab联合仿真 -dds s verilog simulation dds s verilog simulation dds s verilog simulation dds s verilog simulation
Platform: | Size: 283648 | Author: 才一句 | Hits:

[VHDL-FPGA-Verilog] DDS-VERILOG

Description: DDS的信号发生器verilog代码 可直接用于编程 已经测试-Verilog code of the DDS signal generator which can be used directly in the programming has been tested
Platform: | Size: 3072 | Author: 佘琪 | Hits:

[Software Engineering] DDS-Verilog

Description: DDS设计的源代码 用于生成高精度的DDS程序 VERILOG-VERILOG DDS DDS program design source code used to generate high-precision
Platform: | Size: 8192 | Author: hdl | Hits:

[VHDL-FPGA-Verilog] DDS-MY-WORK-1

Description: FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog
Platform: | Size: 10680320 | Author: luowang | Hits:

[VHDL-FPGA-Verilog] DDS-verilog

Description: DDS是直接数字式频率合成器（Direct Digital Synthesizer）的英文缩写，是一项关键的数字化技术。与传统的频率合成器相比，DDS具有低成本、低功耗、高分辨率和快速转换时间等优点，广泛使用在电信与电子仪器领域，是实现设备全数字化的一个关键技术。文件写了一个DDS的例程，并编写了TB文件。-DDS is a direct digital synthesizer (Direct Digital Synthesizer) of the English abbreviation, is a key digital technology. Compared with the traditional frequency synthesizer, DDS has the advantages of low cost, low power consumption, high resolution and fast conversion time. It is widely used in the field of telecommunication and electronic instrument, which is a key technology to realize the whole digitization of equipment. The file was written with a DDS routine and a TB file was written.
Platform: | Size: 2048 | Author: 林威 | Hits:

[VHDL-FPGA-Verilog] dds(1)

Description: 基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
Platform: | Size: 11024384 | Author: 电磁驱动 | Hits:

[VHDL-FPGA-Verilog] DDS波形发生器

Description: DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)
Platform: | Size: 395264 | Author: jacktk@buaa.edu.cn | Hits:
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